In modern chip design, there is an ever present desire to run chips at higher frequencies. Limiting power dissipation is a significant challenge in the design of such circuits. In particular, high power dissipation causes several problems, which include a reduction of the battery life in mobile systems, added cost to packaging, added cost to a cooling solution, and/or the like. Further, power dissipation can cause various circuit problems, and even a chip failure (e.g., due to overheating). Two prominent sources for power dissipation are dynamic power dissipation, which occurs when a device (e.g., transistor, gate, or the like) changes state, and leakage (static) power dissipation, which results when the device allows current to flow through even when it is not switching. As the channel length sizes of transistors used in a circuit are reduced, leakage power dissipation becomes more significant to the overall power consumption of the circuit.
Timing closure is frequently performed as part of designing a circuit. This process involves analyzing each path in the design to determine whether it meets the clock cycle time requirements of the design. If not, the operational speed of one or more components on the path can be improved. The operational speed of a path component can be improved in many ways. A typical approach for improving the speed of a path component involves replacing a higher threshold voltage implementation of the path component with a lower threshold voltage implementation of the component, which operates faster. However, lower threshold voltage implementations leak more power than the higher threshold voltage implementations. As a result, such a replacement generally will increase the amount of leakage in the circuit.
Various solutions exist that seek to perform timing closure while accounting for the amount of leakage. For example, one solution assumes that a larger area is required for a faster implementation of a device. To this extent, the solution uses a measurement derived from a change in the timing and a change in the area between a current implementation and a new implementation. The solution selects the new implementation that provides the best benefit in timing while using the smallest amount of additional area. However, for some implementations, the area versus timing tradeoff does not apply.
To this extent, a need exists for an improved solution for designing a circuit that addresses the problems discussed herein and/or other problems recognizable by one in the art.